1. Field of the Invention
The present invention relates generally to an improved means of implementing a digital phase-lock loop for replacing analog phase-lock loops which use voltage controlled or tuned tank oscillators. The invention also describes a very low jitter IC clock recovery circuit for an Integrated System Digital Network two wire bidirectional interface between a telephone central office line terminal and subscriber network terminals, called the ISDN U interface receiver. The invention is generally applicable to high and low speed transmission multiplexers and subscriber line interface circuits (SLIC's), and to data communications generally.
2. Description of the Prior Art
In the known prior art, digital phase-lock loops required a much higher input clock reference frequency than the desired output frequency to allow small clock phase adjustments to be made at the output. The input clock is divided down to the required output frequency which can be phase corrected by a minimum of one input clock period. Typically, a prior art digital phase-lock loop used in a data clock recovery circuit requires an input reference frequency 10 to 100 times the output clock frequency to provide the desired receiver signal-to-noise performance. For example, a low speed optical fiber DS2 receiver with a 13.056 Mhz Manchester data sampling clock would require an input reference frequency of 208.9 Mhz (16 times the sampling clock frequency) to provide +/-4.8 nsec sampling resolution. In a special application, such as an ISDN U interface echo cancelling clock recovery circuit for 80 kbps, 2BlQ data, a minimum input clock reference frequency of 1000 times the bit rate (80 Mhz) is required to provide adequate cancellation of the transmitted signal and the return echo. The 2BlQ data is a well known format representing 2 binary 1 quaternary wherein two bits are mapped into one baud, with each baud period of 12.5 microseconds containing a four level signal. Manchester encoding is also well known and is accomplished by representing a logic "1" with a (+) followed by a (-), and a logic "0" with a (-) followed by a (+).
There are disadvantages to the aforementioned prior art technique in using high (&gt;25 Mhz) instead of low (&lt;25 Mhz) frequency reference clocks for digital phase-lock loops. The high speed interface circuitry required is more costly, it consumes more power, and it generates more radio frequency interference (RFI). Furthermore, the crystals used for the high frequency reference do not operate in the fundamental mode but rather in harmonic modes and consequently are less efficient and more costly than crystals operating in the fundamental mode. High frequency crystals are also more susceptible to frequency drift due to stray capacitance and humidity. Because of these stability problems, an analog VCO or tuned tank oscillator is generally used in such high frequency applications even though such analog components require initial adjustment or trimming and drift with temperature.
Digital phase-lock loop circuitry is generally well known in the prior art, as exemplified by U.S. Pat. No. 3,585,298, Timing Recovery Circuit with Two Speed Phase Correction; U.S. Pat. No. 3,646,452, Second Order Digital Phase-Lock Loop; U.S. Pat. No. 3,697,689, Fine Timing Recovery System; U.S. Pat. No. 3,777,272, Digital Second-Order Phase-Locked Loop; U.S. Pat. No. 4,288,874, Timing Data Reproduction System; and U.S. Pat. No. 4,400,817, Method and Means of Clock Recovery in a Received Stream of Digital Data.
A further example of the prior art is the digital phase-lock loop used in the NEC uPD9306/A CMOS hard-disk interface IC. This integrated circuit is described in the NEC Microcomputer Products 1987 Data Book Vol. 2 of 2, pages 6-125, 6-126 and 6-127. A delay line with ten 10 nsec taps is required for the described NEC IC, which is not as cost effective as the present invention and does not provide the resolution possible with the present invention, as ten external leads from the delay line must interface the NEC IC.
In contradistinction to the disadvantages of the prior art described by way of example above, the present invention allows the use of an input frequency which is approximately equal to the desired output frequency while yielding output clock phase adjustments as small as two NAND gate propagation delays. For 2 micron CMOS, this is about 4 nsec, which is equivalent to a 250 Mhz reference clock with a conventional digital phase-lock loop. A DS2 Manchester data receiver using the present invention requires only a 13.056 Mhz crystal to provide 4 nsec phase adjustments. An ISDN U interface clock recovery circuit could use a 10.24 Mhz crystal to also provide 4 nsec phase adjustments (1/3125th of a bit period). A 10.24 Mhz phase corrected output is divided by 128 to derive an 80 Khz receive clock. The 10.24 Mhz clock is also used to drive digital signal processing hardware.
There are numerous applications of the present invention, including low speed fiber optic and ISDN clock recovery circuits, and high speed fiber optic data and clock recovery circuits using high speed IC technology. For example, a 500 Mbit/sec NRZ data and clock recovery circuit could be implemented using a 500 Mhz clock reference input to a gallium arsenide IC implementation of the invention. An on-chip 100 psec selector delay would provide a resolution of 20 samples per bit. A prior art digital phase-lock loop would require a very high 10 Ghz clock reference input, instead of the much lower frequency of the present invention.
The present invention is advantageously applicable wherever a digital phase-lock loop can be used, but without the requirement of the prior art for a high frequency reference.
The present invention can also be used to implement a delay line with delay based on a clock reference. The delay is established by a programmable percentage of the average phase retard count. Integrated circuit process delay variations are compensated for upon initialization, but periodic calibration cycles are required to compensate for temperature and voltage changes.